i2c from altera wiki

Hi all

I've downloaded the i2c ip from altera wiki and simulated it in Nios II with ModelSim-Altera.

http://www.alterawiki.com/wiki/opencores_i2c

(http://www.alterawiki.com/wiki/opencores_i2c)

The attached picture is my simulation result.

My problem is why the sda and scl are always 0.

My C code is basically to enable the i2c ip and to send start condition, address(0x3f), and data.

I2C_init(OPENCORES_I2C_BASE, 100000000, 100000);
I2C_start(OPENCORES_I2C_BASE, 0x3f, 0); // 3f << 1
I2C_write(OPENCORES_I2C_BASE, 3, 0);
I2C_write(OPENCORES_I2C_BASE, 0xf0, 1);

From the simulation result, the prescale register becomes 0x00c7 as expected.

(100MHz/5/100KHz-1 = 0x00c7)

The register txr becomes 0x7e which stands for the slave address 0x3f and writing operation.

The status register shows TIP (transfer in progress) but there's no change on the sda and scl signals.

I check "i2c_master_bit_ctrl.v" and find the following code. I guess this is why sda and scal are always 0 but I'm not sure about it.

// assign scl and sda output (always gnd)
assign scl_o = 1'b0;
assign sda_o = 1'b0;

I believe there must be someone who has used this IP successfully.

Should I modify the verilog code and is there anything missing in my design?