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Altera_Forum
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13 years ago

i2c from altera wiki

Hi all I've downloaded the i2c ip from altera wiki and simulated it in Nios II with ModelSim-Altera. http://www.alterawiki.com/wiki/opencores_i2c (http://www.alterawiki.com/wiki/opencor...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I2C is an open-drain protocol, with a pull-up resistor.

scl_padoen_o and sda_padoen_o are only set to '0' when the I2C master needs to transmit a '0'.

When it needs to transmit a '1', they're set to '1' and the pin stays in high-Z, letting the pull-up resistor pull the line to '1'.

That's why the I2C master designers have hard-wired sda_pad_o and scl_pad_o to '0'.

To simulate an I2C bus using Verilog, in addition to that assignment you showed, you need to use "tri1" signals for SCL and SDA. These will go to "weak high" when you drive them to 'Z'.