I would like to know the required voltage level (VCCR_GXB and VCCT_GXB) for the tranceiver and receiver bank of the 10AS022C3U19I2SG to support PCIe Gen.3.

Hie,

The required voltage level (VCCT_GXB and VCCT_GXB) for transceiver and receiver of Arria 10 device (10AS022C3U19I2SG) to support PCIe Gen3 is 1.03V. This information is documented both in Pin Connection Guideline as you have observed and in Arria 10 Datasheet.(Table 4 - refer to note 19)

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_datasheet.pdf

The information in Transceiver Phy User Gude pg 255 shows the configuration options only for Transceiver Native Phy IP to use PCIe in PIPE mode. Selecting this options will not step up/step down the voltage at the Rx buffer or Tx buffer. This 1_1V, 1_0V, 0_9V options only used for GUI rule validation to provide a message in the System Messages" window in the Transceiver Native Phy IP based on your other configuration selection. This is described in Table 9 -pg 48 of Arria 10 Transceiver Phy user guide.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf

Another rule check is on the Quartus Prime fitter which requires you to specify 1_0V or 1_1V using assignment editor or pin planner or qsr when configuring PCIe Gen3. However, this are just rule checks and does not change the actual voltage requirement on VCCR_GXB or VCCT_GXB.

Hence, the power supply required to be used is 1.03V as indicated in Arria 10 Pin Connection Guidelines and Datasheet. For the GUI election, please use 1_0V and qsf assignment use 1_0V as well.

Using 0.95V will reduce the jitter performance on both Transmitter and Receiver side. Hence, PCIe electrical full compliance might not be met resulting potential functional and performance issues.

Regards,

Nathan