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Jacob11's avatar
Jacob11
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

I need a scheme to max out the DSP blocks on a Stratix 10

Hello guys, I am working on a design to use all 3000 DSP blocks on the stratix 10 FPGA. I thought the best solution would be to instantiate this intel fixed point DSP IP as a multiplier: https:...
  • Jacob11's avatar
    Jacob11
    3 years ago

    SOLVED!!!!

    I was assigning the output registers of each DSP block incorrectly.

    What I had:


    assign result1_a_r[i] = result1_a[i];
    assign result1_b_r[i] = result1_b[i];

    What it should be:

    always @(posedge clk_i) begin
    result1_a_r[i] <= result1_a[i];
    result1_b_r[i] <= result1_b[i];
    end
    I replaced this code in each of the chained DSP blocks and now I have it running up to 3000 DSP blocks.
    Thanks
    Jacob
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Jacob,


I’m glad that your problem has been solved, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey


Regards,

Nurina