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Jacob11's avatar
Jacob11
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

I need a scheme to max out the DSP blocks on a Stratix 10

Hello guys, I am working on a design to use all 3000 DSP blocks on the stratix 10 FPGA. I thought the best solution would be to instantiate this intel fixed point DSP IP as a multiplier: https:...
  • Jacob11's avatar
    Jacob11
    3 years ago

    SOLVED!!!!

    I was assigning the output registers of each DSP block incorrectly.

    What I had:


    assign result1_a_r[i] = result1_a[i];
    assign result1_b_r[i] = result1_b[i];

    What it should be:

    always @(posedge clk_i) begin
    result1_a_r[i] <= result1_a[i];
    result1_b_r[i] <= result1_b[i];
    end
    I replaced this code in each of the chained DSP blocks and now I have it running up to 3000 DSP blocks.
    Thanks
    Jacob
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Sorry for the late response, can you share your .qar file? To do this, go to Project>Archive Project.


Regards,

Nurina


  • Jacob11's avatar
    Jacob11
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hello Nurina,

    Attached is the .qar file.

    I have commented out the last 2 DSP blocks in the chain to give a total DSP load of 450 blocks. This design builds fine(although it fails timing).

    I recommend that you start with this build, and then comment out lines 499-502 and uncomment the block from lines 504-554. This will bring the total DSP count to 510 and the build will fail.

    I cannot figure a way around this 468 bottleneck. I even tried instantiating another IP, the floating point DSP IP to split the load. No matter how I combined the fixed point and floating point IP's there was nothing I could do to achieve more than 468 DSP blocks.

    Thanks

    Jacob