Jacob11
Occasional Contributor
Occasional ContributorI need a scheme to max out the DSP blocks on a Stratix 10
Hello guys,
I am working on a design to use all 3000 DSP blocks on the stratix 10 FPGA. I thought the best solution would be to instantiate this intel fixed point DSP IP as a multiplier:
https:...
SOLVED!!!!
I was assigning the output registers of each DSP block incorrectly.
What I had:
assign result1_a_r[i] = result1_a[i];
assign result1_b_r[i] = result1_b[i];What it should be:
always @(posedge clk_i) beginresult1_a_r[i] <= result1_a[i];result1_b_r[i] <= result1_b[i];endI replaced this code in each of the chained DSP blocks and now I have it running up to 3000 DSP blocks.ThanksJacob
