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Jacob11
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

I need a scheme to max out the DSP blocks on a Stratix 10

Hello guys, I am working on a design to use all 3000 DSP blocks on the stratix 10 FPGA. I thought the best solution would be to instantiate this intel fixed point DSP IP as a multiplier: https:...
  • Jacob11's avatar
    Jacob11
    3 years ago

    SOLVED!!!!

    I was assigning the output registers of each DSP block incorrectly.

    What I had:


    assign result1_a_r[i] = result1_a[i];
    assign result1_b_r[i] = result1_b[i];

    What it should be:

    always @(posedge clk_i) begin
    result1_a_r[i] <= result1_a[i];
    result1_b_r[i] <= result1_b[i];
    end
    I replaced this code in each of the chained DSP blocks and now I have it running up to 3000 DSP blocks.
    Thanks
    Jacob
Jacob11's avatar
Jacob11
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hello Nurina,

The output issue is solved by this trick, but i got bottlenecked at 468 DSP blocks.

I also tried chaining a lot of DSP blocks together (output from block1 as input of block2). This also works until I reach 468 DSP blocks. Then the place and route process fails with the message:

Error(184036): Cannot place the following 57 DSP cells -- a legal placement which satisfies all the DSP requirements could not be found
Info(184037): Node "GEN_DSP_2[0].U_DSP|s10_native_fixed_point_dsp_0|fourteennm_mac_component"
Info(184037): Node "GEN_DSP_2[132].U_DSP|s10_native_fixed_point_dsp_0|fourteennm_mac_component"
Info(184037): Node "GEN_DSP_2[133].U_DSP|s10_native_fixed_point_dsp_0|fourteennm_mac_component"
Info(184037): Node "GEN_DSP_2[134].U_DSP|s10_native_fixed_point_dsp_0|fourteennm_mac_component"
Info(184037): Node "GEN_DSP_2[135].U_DSP|s10_native_fixed_point_dsp_0|fourteennm_mac_component"
Info(184037): Node "GEN_DSP_2[136].U_DSP|s10_native_fixed_point_dsp_0|fourteennm_mac_component"
Info(184037): Node "GEN_DSP_2[137].U_DSP|s10_native_fixed_point_dsp_0|fourteennm_mac_component"
Info(184037): Node "GEN_DSP_2[138].U_DSP|s10_native_fixed_point_dsp_0|fourteennm_mac_component"
Info(184037): Node "GEN_DSP_2[139].U_DSP|s10_native_fixed_point_dsp_0|fourteennm_mac_component"
Info(184037): Node "GEN_DSP_2[140].U_DSP|s10_native_fixed_point_dsp_0|fourteennm_mac_component"
Info(18798): And 47 more similar nodes (full list omitted for brevity)

Here is the important parts of the updated code:

module power_test_design (
input wire clk_i,
output wire [NUM_DSP_BLOCKS-1:0] output0,
output wire [NUM_DSP_BLOCKS-1:0] output1,
output wire [NUM_DSP_BLOCKS-1:0] output2
);

localparam NUM_DSP_BLOCKS = 175;
wire [36:0] result0_a [NUM_DSP_BLOCKS-1:0];
wire [36:0] result0_b [NUM_DSP_BLOCKS-1:0];
wire [36:0] result1_a [NUM_DSP_BLOCKS-1:0];
wire [36:0] result1_b [NUM_DSP_BLOCKS-1:0];
wire [36:0] result2_a [NUM_DSP_BLOCKS-1:0];
wire [36:0] result2_b [NUM_DSP_BLOCKS-1:0];
//generate DSP chain
generate
for (i=0; i<NUM_DSP_BLOCKS; i=i+1) begin : GEN_DSP_0

dsp_fixed U_DSP (
.ay ($unsigned(ay_r)), // input, width = 18, ay.ay
.by ($unsigned(by_r)), // input, width = 18, by.by
.ax ($unsigned(ax_r)), // input, width = 18, ax.ax
.bx ($unsigned(bx_r)), // input, width = 18, bx.bx
.resulta (result0_a[i]), // output, width = 37, result0_a.result0_a
.resultb (result0_b[i]), // output, width = 37, result1.result1
.clk0 (clk_i), // input, width = 1, clk0.clk
.clk1 (), // input, width = 1, clk1.clk not used
.clk2 (), // input, width = 1, clk2.clk not used
.ena (ena_r) // input, width = 3, ena.ena
);
assign output0[i] = result0_a[i][0];
end
endgenerate
generate
for (i=0; i<NUM_DSP_BLOCKS; i=i+1) begin : GEN_DSP_1

dsp_fixed U_DSP (
.ay (result0_a[i][17:0]), // input, width = 18, ay.ay
.by (result0_b[i][17:0]), // input, width = 18, by.by
.ax (result0_a[i][17:0]), // input, width = 18, ax.ax
.bx (result0_b[i][17:0]), // input, width = 18, bx.bx
.resulta (result1_a[i]), // output, width = 37, result0_a.result0_a
.resultb (result1_b[i]), // output, width = 37, result1.result1
.clk0 (clk_i), // input, width = 1, clk0.clk
.clk1 (), // input, width = 1, clk1.clk not used
.clk2 (), // input, width = 1, clk2.clk not used
.ena (ena_r) // input, width = 3, ena.ena
);

assign output1[i] = result1_a[i][0];
end
endgenerate

generate
for (i=0; i<NUM_DSP_BLOCKS; i=i+1) begin : GEN_DSP_2

dsp_fixed U_DSP (
.ay (result1_a[i][17:0]), // input, width = 18, ay.ay
.by (result1_a[i][17:0]), // input, width = 18, by.by
.ax (result1_b[i][17:0]), // input, width = 18, ax.ax
.bx (result1_b[i][17:0]), // input, width = 18, bx.bx
.resulta (result2_a[i]), // output, width = 37, result0_a.result0_a
.resultb (result2_b[i]), // output, width = 37, result1.result1
.clk0 (clk_i), // input, width = 1, clk0.clk
.clk1 (), // input, width = 1, clk1.clk not used
.clk2 (), // input, width = 1, clk2.clk not used
.ena (ena_r) // input, width = 3, ena.ena
);
assign output2[i] = result2_a[i][0];
end
endgenerate
Then for the assignment editor it looks like this:
Unfortunately, I still get the error message:
Error(184036): Cannot place the following 57 DSP cells -- a legal placement which satisfies all the DSP requirements
could not be found

If I lower the "NUM_DSP_BLOCKS localparam" until the total DSP blocks are less than 468, the project successfully
compiles through to the assembler stage. If its more than 468 in total, no matter how i configure this thing
I get this error message. It synthesizes fine, but fails place and route.
I have tried just doing one big block of 500 DSP generates, and I have tried chaining together 20 DSP generates
that generate only 30 each. All of it bottlenecks at 468. There is some kind of limitation here, but the error message
is not meaningful enough for me to understand.
Any other ideas??
Thanks,
Jacob