I am trying to create a Viterbi IP block and use in my Arria V GZ design. I am not running an Avalon bus internal. I see that when I choose the Viterbi IP from the DSP/Error Detection and Correction section, it is generated using Qsys.

Hi Glenn,

Thanks for your update. As I understand it, you are using Viterbi IP in Continous Mode. For your information, I have tested configuring the Viterbi IP in Continous Mode (left other settings as default) and generated the example design from the IP in Q17.0Std. Note that I do not have AV database installed in my local PC and therefore I am generating for CV devices.

After generating the design, I do the following to simulate the example design:

1. Open Modelsim and change working directory to the "simulation_scripts\mentor"

2. Type "source msim_setup.tcl"

3. Type "ld" to start compilation

4. Add the targeted signals to Wave and run the simulation

For your information, the simulation seems to be working fine. I have emailed you the simulation example (viterbi_ii_0_ex_des_cont.zip) that I am running for your reference.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin