HPC Memory Controller Write but can't Read

1 - You have a clock that's not connected.

:confused:pll_ref_clk is a 100MHz clock being fed into the core. Core is configured for a half-rate bridge already so effective 200Mhz with 32-bit data. All other clocks are outputs so I have listed those as 'open' in the instantiations (aux_full/half_rate_clk, phy_clk, dll_ref_clk)

2 - You have a reset that's not connected or is improperly connected (logic high vs. logic low).

:confused: global_reset_n is connected to the system reset, which is also active low. soft_reset_n is tied to '1' in the instantiation because it is not being used.

3 - The HPC controller is not coming out of reset because it can't initialize the RAM. Are you using a DDR controller?

:confused: The HPC controller is the DDR2 controller. Are you inferring I need another controller? The interfaces that are created during the SOPC generate process are the correct ones for our DDR2 we are using.

4 - Are you running through a clock-crossing bridge? Did you verify that you are meeting all timing requirements?

:confused:No clock-crossing bridge in the system. According to Time Quest all constraints and requirements are being met.

pinscore