--- Quote Start ---
We had the very same problems and it turned out that it is the same root cause. Thanks for sharing your thoughts and solution with this issue!
--- Quote End ---
I agree :). Posting stuff like this is very helpful for others (like me). I just got a board back with the same problem. Apparently the .pin file will not tell you to connect VREF to 0.75V if mem_clk, but no other SSTL "inputs", are in a bank. Anyway, we found another workaround that I am attaching to this post. (BTW our design uses DDR3 not DDR2.)
There must be a reason for them using the single ended buffer, so I don't think this workaround is good forever, but it is acceptable for testing your design until you get your re-worked board.
Regards,
Keith
Honored Contributor
