HP DDR2 Controller fails Calibration/Initialization

Update:

I may have found a possible error (and possible cause for problem described above) in the circuit:

VREF for bank 8 is not connected, at first I thought this wouldn't be a problem because all inputs that use the SSTL 18 CLASS I i/o standard are connected to bank 7 of which the VREF pin is connected.

The DDR2 CLK is connected to bank 8 and I realized that the DDR2 controller IP uses the input buffer to read back the clock to compensate for delays (MIMIC path), so VREF for this bank should also be connected. I think this would explain the initialization failure..

Now I'll just have to wait for the boardrevision to come in.

I'll post a confirmation when I've confirmed that this was the problem.

Cheers,

Olaf