Forum Discussion
FvM
Super Contributor
2 years agoHello,
the question involves a misunderstanding. FPGA configuration (and, if present, embedded processor code) stored in EPCS memory is not executed in user mode, it's loaded to FPGA internal memory after power on reset. EPCS memory can be read and written in user mode, e.g. through ASMI Parallel IP core.
Secondly, Quartus programmer only erases or overwrites the flash sectors specified in .jic file, unless you perform an intentional full erase operation.
Regards,
Frank