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Occasional ContributorHow to switch the HDMI PHY reference clock to the HDMI Rx TMDS clock ?
Hi Wincent_Altera,
Thanks for the answer at 2024-12-29.
Please bear with me for the long comment below, but I like to document the effort I have gone through to determine how to use the HDMI PHY RX IP block, since it appears that I am either missing something, or the HDMI PHY RX IP block does not provided the shortcut to a HDMI implementation that I originally expected.
In the HDMI example project I found the file "intel_hdmi_rx_phy.c" (attached for reference) with the function "intel_hdmi_rx_phy_switch_ref_clock".
In the document "HDMI PHY Intel FPGA IP Design Example User Guide" at link https://www.intel.com/content/www/us/en/docs/programmable/732781/22-2-1-0-0/phy-design-example-quick-start-guide.html, I looked for references to the file "intel_hdmi_rx_phy.c" or function "intel_hdmi_rx_phy_switch_ref_clock", but could not find any, so I assume there is no documentation of the file nor function.
When reverse engineering the function "intel_hdmi_rx_phy_switch_ref_clock", I found use of addresses based on the file "intel_hdmi_rx_phy_regs.h" (attached for reference), where the relevant addresses are in the ranges:
0x0000 - 0x0FFF for INTEL_HDMI_RX_PHY_RCFG_MGMT
0x1000 - 0x1FFF for INTEL_HDMI_RX_PHY_MEASURE_PIO
The addresses in range 0x1000 - 0x1FFF for INTEL_HDMI_RX_PHY_MEASURE_PIO are described in the document "HDMI PHY Intel FPGA IP User Guide" section "5.1.5. RX PHY Address Map" link https://www.intel.com/content/www/us/en/docs/programmable/732147/22-3-1-0-1/rx-phy-address-map-21037.html.
The addresses in range 0x0000 - 0x0FFF for INTEL_HDMI_RX_PHY_RCFG_MGMT are described as "Transceiver Avalon reconfiguration bus" in the section "5.1.5. RX PHY Address Map", where the specific addresses used in the function "intel_hdmi_rx_phy_switch_ref_clock" from the file "intel_hdmi_rx_phy_regs.h" are:
INTEL_HDMI_RX_PHY_RCFG_MGMT_ACCESS: INTEL_HDMI_RX_PHY_RCFG_MGMT + 0x000
INTEL_HDMI_RX_PHY_RCFG_MGMT_CDR_REFCLK_W: INTEL_HDMI_RX_PHY_RCFG_MGMT + 0x504
INTEL_HDMI_RX_PHY_RCFG_MGMT_CDR_REFCLK_R: INTEL_HDMI_RX_PHY_RCFG_MGMT + 0x5ACThe offset addresses, for example 0x504, requires reference to the document "Arria 10 Transceiver PHY User Guide" at link https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/transceiver-phy-overview.html, with further reference to the section "6.19. Arria 10 Transceiver Register Map" at link https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/transceiver-register-map.html which has reference to the Excel sheet "Arria 10 Transceiver Register Map" at link https://www.altera.com/content/dam/altera-www/global/en_US/others/literature/hb/arria-10/a10_registermap.xlsx. The address offset reference in "intel_hdmi_rx_phy_regs.h", for example 0x504, must be divided by 4 due to 32-bit access by NIOS CPU and decoded as PMA reference to give the address C.0x141, for which documentation can then be found in that Excel sheet.
Having the decoded address C.0x141 I was further able to find additional reference to offset 0x141 in document "Arria 10 Transceiver PHY User Guide" section "6.11.2.3. CDR and CMU Reference Clock Switching" at link https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/cdr-and-cmu-reference-clock-switching.html, with description of the reference clock switching.
Please let me know if I missed some description in the document "HDMI PHY Intel FPGA IP User Guide", but it appears that the answer to my original question "How to switch the HDMI PHY reference clock to the HDMI Rx TMDS clock ?" at 2024-12-03 requires reverse engineering of the example design as described above, based on your reference to file and function, and further detailed knowledge about the transceivers and the related document "Arria 10 Transceiver PHY User Guide".
Also, please let me know, if reference clocks to switch between in the HDMI PHY RX IP block is documented anywhere, except in the example project file "intel_hdmi_rx_phy.c" function "intel_hdmi_rx_phy_switch_ref_clock", where it can be determined by reverse engineering the address offset used to read the lookup values in the transceiver Extended Register Map.
Please be assured that I appreciate your effort and continuous support, and it looks like the issue is almost resolved, however with the likely conclusion that the HDMI PHY RX IP block does not wrap the complexity of the transceiver as was my original impression.
Regards,
M_DK_FPGA
Occasional ContributorHi Wincent_Altera,
Thanks for looking into this question.
There was some amount of new material for me to look at, so I did not answer right away.
However, even though the example in AN-776 is comprehensive, and covering much more than only the HDMI RX PHY part I look at, there was no where in the Rx register map in appendix "A. HDMI RX Interface Register Map" where I could find information about how to change the clock between reference clock and HDMI Rx clock in the HDMI RX PHY.
I have attached image with Figure 4 from the HDMI RX PHY documentation, where the text under the image says "Allows software to switch the transceiver reference clock from the fr_clk to the rx_tmds_clk.". However, I was unable to find information in the PHY RX document about the mechanism that provides this ability to switch between the clocks.
Question: How to switch the HDMI PHY reference clock to the HDMI Rx TMDS clock ?
Thanks in advance for your support.
Best regards
M_DK_FPGA
Regular ContributorHi,
TMDS clock must also drive the transceiver dedicated reference clock pin.
If the TMDS clock pin is routed to the transceiver dedicated reference clock pin
you only need to create one transceiver reference clock input.
You can use the TMDS clock as reference clock for a generic core PLL to drive the transceiver
Regards,
Wincent
- M_DK_FPGA
Hi Wincent,
Thanks for the reply.
Just to be sure, and make your comment apply to the HDMI PHY Rx that I am working on.
Question: Are you saying that I should connect the HDMI Rx clock to both the HDMI PHY Rx clock input on port fr_clk and port rx_tmds_clk ?
Question: If the clock is to be the same, why is software allowed to switch the transceiver reference clock from the fr_clk to the
rx_tmds_clk ?I cant make that fit with the description of below Figure 4 (attached in my answer 2024-12-10), where the text says "RX PHY includes a free running fr_clk as reference clock 0 to handle the specific HDMI use case where there is no refclk to the transceiver due to the HDMI cable not plugged in (refclk to the transceiver comes from the HDMI RX connector). Without refclk transceiver input, power-up calibration takes longer to complete.".
Also, the fr_clk is required to be in the range from 61 to 800 MHz, as described in doc ug_hdmi_phy page 17, but when the HDMI input is for example VGA 640 x 480 at 60 Hz the HDMI clock is only about 25 MHz.
Regards
M_DK_FPGA
- Wincent_Altera
Hi DK,
You should provide different TMDS Clock frequencies to HDMI Tx refclk required for your application like 148.5,148.35, 74.25 and 74.18MHz- TMDS clk that connect to FPGA PLL refclk will vary depend on video resolution as you are aware now so you can't set it to some fixed clk frequency.
- For HDMI Rx, TMDS clk will come from external HDMI cable
- For HDMI Tx, in HDMI example design we tied it back to HDMI Rx TMDS clk for ease of demo purpose but for your own application that required to run different video resolution for HDMI Tx and Rx separately, you should provide separate TMDS clk for your HDMI Tx
- When PLL refclk that carry TMDS clk frequency changes too much, HDMI IP example design reconfig controller design will reconfig PLL and transceiver to match with this new TMDS clk range
- You can refer to page 63, figure 23 Multi-Rate Reconfiguration Sequence Flow for HDMI Rx
- You can refer to page 67, figure 24 Reconfiguration Sequence Flow for HDMI Tx
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-hdmi-de.pd
- HDMI Tx/Rx ls_clk and vid_clk frequency calculation is available in page 72, table 40 clocking scheme signals
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-hdmi-de.pd
Regards,
Wincent- M_DK_FPGA
Hi Wincent,
Thanks for the answer.
For now I am only interested in HDMI Rx, so I would appreciate if we can concentrate on that, in order to focus the attention
To address the points from you mail, please see my comments below.
However, after reading the points, my original question is still pending, so may I kindly ask you to take a look at this question related to use of Altera IP HDMI Rx PHY, described in document "HDMI PHY Intel FPGA IP User Guide" ID ug_hdmi_phy version 2022.10.31, where the text and first bullet below "Figure 4. HDMI RX PHY Architecture" (attached) says:
"The HDMI RX PHY performs the following main functions: * Allows software to switch the transceiver reference clock from the fr_clk to the rx_tmds_clk."
Question: How to switch the HDMI PHY reference clock to the HDMI Rx TMDS clock, as the bullet says in "Allows software to switch the transceiver reference clock from the fr_clk to the rx_tmds_clk." ?
Comments to the previous answer.
> You should provide different TMDS Clock frequencies to HDMI Tx refclk required for your application like 148.5,148.35, 74.25 and 74.18MHz
HDMI Tx is not relevant now, but I agree that the IP HDMI TX PHY has clock input port tx_tmds_clk for HDMI Tx TMDS clock and clock input port fr_clk Free-running clock for transceiver power-up calibration.
> * TMDS clk that connect to FPGA PLL refclk will vary depend on video resolution as you are aware now so you can't set it to some fixed clk frequency.
> * For HDMI Rx, TMDS clk will come from external HDMI cableAgree, I have connected that the input HDMI Rx TMDS clock.
> * For HDMI Tx, in HDMI example design we tied it back to HDMI Rx TMDS clk for ease of demo purpose but for your own application that required to run different video resolution for HDMI Tx and Rx separately, you should provide separate TMDS clk for your HDMI TxI have not dug into HDMI Tx in the design example, since I do not have a HDMI Tx in my current design.
> * When PLL refclk that carry TMDS clk frequency changes too much, HDMI IP example design reconfig controller design will reconfig PLL and transceiver to match with this new TMDS clk rangeI am uncertain what PLL refclk is referred to here, but if it is HDMI Rx, then I see your point, since that comes from the input HDMI Rx TMDS clock.
> * You can refer to page 63, figure 23 Multi-Rate Reconfiguration Sequence Flow for HDMI RxI assume this reference is to the document "HDMI Arria 10 FPGA IP Design Example User Guide" ID UG-20077, where the newest version 2024.04.29 has "Figure 23. Multi-Rate Reconfiguration Sequence Flow" on page 62.
However, this example design uses the native transceivers (GXB), as it can be seen page 12 and 13, thus not the Altera IP HDMI Rx PHY block that my question is about.
The Altera IP HDMI Rx PHY block actually handles the reconfiguration internally, as described in document "HDMI PHY Intel FPGA IP User Guide" ID ug_hdmi_phy version 2022.10.31 below "Figure 4. HDMI RX PHY Architecture" in bullet 2 and 3:
* Reconfig Management block measures frequency of the incoming HDMI TMDS clock (rx_tmds_clk) to determine the received video pixel rate.
* Reconfigures the RX transceivers according to the received video pixel rate.
> * You can refer to page 67, figure 24 Reconfiguration Sequence Flow for HDMI Tx
> * https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-hdmi-de.pd
> * HDMI Tx/Rx ls_clk and vid_clk frequency calculation is available in page 72, table 40 clocking scheme signals
> * https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-hdmi-de.pdAs described above, then Tx is not relevant for my design right now, and the design example uses the native transceiver, thus not the Altera IP HDMI Rx PHY that I use, and which is actually a more recent way of doing the HDMI Rx.
Regards
M_DK_FPGA
- TMDS clk that connect to FPGA PLL refclk will vary depend on video resolution as you are aware now so you can't set it to some fixed clk frequency.
