How to switch the HDMI PHY reference clock to the HDMI Rx TMDS clock ?

Hi Wincent_Altera,

Thanks for the answer at 2024-12-29.

Please bear with me for the long comment below, but I like to document the effort I have gone through to determine how to use the HDMI PHY RX IP block, since it appears that I am either missing something, or the HDMI PHY RX IP block does not provided the shortcut to a HDMI implementation that I originally expected.

In the HDMI example project I found the file "intel_hdmi_rx_phy.c" (attached for reference) with the function "intel_hdmi_rx_phy_switch_ref_clock".

In the document "HDMI PHY Intel FPGA IP Design Example User Guide" at link https://www.intel.com/content/www/us/en/docs/programmable/732781/22-2-1-0-0/phy-design-example-quick-start-guide.html, I looked for references to the file "intel_hdmi_rx_phy.c" or function "intel_hdmi_rx_phy_switch_ref_clock", but could not find any, so I assume there is no documentation of the file nor function.

When reverse engineering the function "intel_hdmi_rx_phy_switch_ref_clock", I found use of addresses based on the file "intel_hdmi_rx_phy_regs.h" (attached for reference), where the relevant addresses are in the ranges:

0x0000 - 0x0FFF for INTEL_HDMI_RX_PHY_RCFG_MGMT

0x1000 - 0x1FFF for INTEL_HDMI_RX_PHY_MEASURE_PIO

The addresses in range 0x1000 - 0x1FFF for INTEL_HDMI_RX_PHY_MEASURE_PIO are described in the document "HDMI PHY Intel FPGA IP User Guide" section "5.1.5. RX PHY Address Map" link https://www.intel.com/content/www/us/en/docs/programmable/732147/22-3-1-0-1/rx-phy-address-map-21037.html.

The addresses in range 0x0000 - 0x0FFF for INTEL_HDMI_RX_PHY_RCFG_MGMT are described as "Transceiver Avalon reconfiguration bus" in the section "5.1.5. RX PHY Address Map", where the specific addresses used in the function "intel_hdmi_rx_phy_switch_ref_clock" from the file "intel_hdmi_rx_phy_regs.h" are:

INTEL_HDMI_RX_PHY_RCFG_MGMT_ACCESS: INTEL_HDMI_RX_PHY_RCFG_MGMT + 0x000
INTEL_HDMI_RX_PHY_RCFG_MGMT_CDR_REFCLK_W: INTEL_HDMI_RX_PHY_RCFG_MGMT + 0x504
INTEL_HDMI_RX_PHY_RCFG_MGMT_CDR_REFCLK_R: INTEL_HDMI_RX_PHY_RCFG_MGMT + 0x5AC

The offset addresses, for example 0x504, requires reference to the document "Arria 10 Transceiver PHY User Guide" at link https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/transceiver-phy-overview.html, with further reference to the section "6.19. Arria 10 Transceiver Register Map" at link https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/transceiver-register-map.html which has reference to the Excel sheet "Arria 10 Transceiver Register Map" at link https://www.altera.com/content/dam/altera-www/global/en_US/others/literature/hb/arria-10/a10_registermap.xlsx. The address offset reference in "intel_hdmi_rx_phy_regs.h", for example 0x504, must be divided by 4 due to 32-bit access by NIOS CPU and decoded as PMA reference to give the address C.0x141, for which documentation can then be found in that Excel sheet.

Having the decoded address C.0x141 I was further able to find additional reference to offset 0x141 in document "Arria 10 Transceiver PHY User Guide" section "6.11.2.3. CDR and CMU Reference Clock Switching" at link https://www.intel.com/content/www/us/en/docs/programmable/683617/21-1/cdr-and-cmu-reference-clock-switching.html, with description of the reference clock switching.

Please let me know if I missed some description in the document "HDMI PHY Intel FPGA IP User Guide", but it appears that the answer to my original question "How to switch the HDMI PHY reference clock to the HDMI Rx TMDS clock ?" at 2024-12-03 requires reverse engineering of the example design as described above, based on your reference to file and function, and further detailed knowledge about the transceivers and the related document "Arria 10 Transceiver PHY User Guide".

Also, please let me know, if reference clocks to switch between in the HDMI PHY RX IP block is documented anywhere, except in the example project file "intel_hdmi_rx_phy.c" function "intel_hdmi_rx_phy_switch_ref_clock", where it can be determined by reverse engineering the address offset used to read the lookup values in the transceiver Extended Register Map.

Please be assured that I appreciate your effort and continuous support, and it looks like the issue is almost resolved, however with the likely conclusion that the HDMI PHY RX IP block does not wrap the complexity of the transceiver as was my original impression.

Regards,

M_DK_FPGA