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DChak3's avatar
DChak3
Icon for New Contributor rankNew Contributor
6 years ago

How to simulate the hard IP libraries in cadence

HI I have created a QSYS design containing nios processor, emif IP, PCIE, etc. Design got synthesized. Now I want to check the design in cadence for which I generated Atlera as well as hard IP librar...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

I will proceed with case closure as the user has found the solution.

I will describe the issue detail below for reference.

Description: The ncsim was run in 32 bit while the libraries were compiled in 64 bit. Thus, it is not compiling the libraries.