How to set Number of Pages and Size if Address page in PCIe (Qsys)

Eh? Are you confusing the configuration of the hardware that generates PCIe cycles with the BARs?

The size of BAR is automatically set so that it is large enough to allow another PCIe master to access any of the connected Avalon slaves.

The PCIe slave logic looks at the high address bits in a received PCIe transfer to determine which BAR it is for, then uses the low bits as an offset within the selected Avalon slave. If the BAR references multiple Avalon slaves then high Avalon address bits will be generated if they are not needed to select between the Avalon slaves.