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Altera_Forum
Honored Contributor
12 years agoHi GZoinker,
According your explanation and the PCIe CORE manual, I have did some configurations on my system and it is working now, but I don't know if I understood how to set this parameters. I will try explain my system and the configurations that I did, and if you could check what I did I will really appreciate. 4 BARS configured - BAR1_0 => 64 bits - BAR2 => 32 bits - BAR3 => 32 bits So I set 4 pages, because I have 4 BARS, is it right? I mapped the addresses of the slaves using the following number of bits (BAR0_1 => 11 bits, BAR2 => 12 bits, BAR3 => 11 bits). So looking the PCIe IP MANUAL, I realized that I could use the the Size of Address Page as 18bits (256kBytes), because: Slave Base Address => 12bits. High => 2 bits (4 Address Page) Low => 18 bits (Size Address Page) In order to have 32 Avalon Address bits. I did this configurations and my system is now working. Is this correct? I'm thinking the right way? Thanks for helping Filipe