How to realize the pipeline in mixed operation of the divider or multiplication?

I am interested in pipeline operation in LPM_divide :

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Assume the result (x/y) need 1.5 clocks and I set the lpm_divide.lpm_pipeline = 3,

Does it mean the lpm_divide just shift register the result with 3 clocks,

or sample the result at each clock edge for 3 clocks?

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No answer yet. Not enough information provided by altera PDFs

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But if it's sampling the result for 3 clocks and get the right result at the last clock edge, i cannot imagine how does the LPM_DIVIDE pipeline realize.

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You can "sample" every 3 clock cycles with D Flip-Flop with Enable and a very small state machine.

In my design, I use pipelined LPM_DIVIDE megafunction provided by quartus.

I arrange in order numerator to change at every 3 clock cycle only.

To do that, I ( I mean Quartus :) ) make a minimal state machine.

But I still interested in how pipeline work in LPM_DIVIDE.

An other point : Quartus synthesizer employ embedded mult. if they are available in the target chip.

excuse for my english, i'm french.