How to realize the pipeline in mixed operation of the divider or multiplication?

I basically don't understand your consideration regarding pipeline operation. If the timing constraints are met, you can expect correct results at the output for each clock cycle. The result is delayed by the specified number of clocks, that's the whole story.

There are no unstable results at the output, except for glitches outside the time window, during that the results are processed by the suceeding logic.

Your Fmax analysis shows that the divider could operate in one clock cycle. Resource usage is always minimal for a non-pipelined solution, timing may be different. I have no particular explaination, why the pipeline=1 solution is as bad, but actually, I don't need an explaination, I guess, you also don't.

One point to be considered: A non-pipelined divider may borrow part of it's logic delay budget from the source and target registers, if they have plenty of timing margin. So the results probably depend on the complete datapath structure.