How to realize the pipeline in mixed operation of the divider or multiplication?

Thanks all. wronghorizon's suggestion is very good. I have another question.

How does the pipeline work in LPM_DIVIDE? LPM_DIVIDE can only be synthesized into combinational logic,

Assume the result (x/y) need 1.5 clocks and I set the lpm_divide.lpm_pipeline = 3,

Does it mean the lpm_divide just shift register the result with 3 clocks,or sample the result at each clock edge for 3 clocks?

If it's shift register, i thinks the result at the last pipeline clock may not be the right result.Because it will shift every unstable result.

But if it's sampling the result for 3 clocks and get the right result at the last clock edge, i cannot imagine how does the LPM_DIVIDE pipeline realize.

Futhermore,I find a strange thing in LPM_DIVIDE synthesis.

for example, do f = (x[7:0]/y[3:0]+a[7:0])/z[3:0] in my pipeline idea on EP2S60F1020C4, the synthesis result vs. pipeline stage:

lpm_pipeline ALUTs ALMs registers memory bits Acutal Fmax

0 127(13) 74(18) 32(32) 0 >500MHz

1 126(12) 88(28) 77(44) 0 168MHz

3 130(9) 97(20) 121(34) 20 199M

5 126(8) 114(23) 176(43) 36 264M

10 154(49) 152(10) 259(15) 140 329M

when use lpm_pipeline=0 , why is the resource and the frequecy best?