How to realize the pipeline in mixed operation of the divider or multiplication?

1) Whether one multiplication or division operation can be done in one clock?

The multiplication or division operation is not register based operation, they are combination logic operation, the clock you used just clock the operation result to a register. The following code has been validated when the clock is running at 10Mhz.

ENTITY Y_BOX_cell IS

PORT (clk: in std_logic;

k: in std_logic_vector (15 downto 0)

b: in std_logic_vector (15 downto 0);

x: in std_logic_vector (15 downto 0);

result: out std_logic_vector (15 DOWNTO 0);

END Y_BOX_cell;

ARCHITECTURE rtl OF Y_BOX_cell IS

signal b_int,x_int,x_int1 : signed (15 downto 0);

signal k_int : signed (15 downto 0);

signal pdt_int : signed (31 downto 0);

BEGIN

Process(clk)

Begin

if clk'event and clk='1' then

k_int <= signed (k);

b_int <= signed (b);

x_int <= signed (x);

x_int1 <= x_int - b_int;

pdt_int <= k_int * x_int1;

result <= std_logic_vector(pdt_int(31)& pdt_int(27 downto 13)

end if;

end process;

END rtl;