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Altera_Forum
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17 years ago

How to realize the pipeline in mixed operation of the divider or multiplication?

If I want to calculate the following function: f = (x * y + a) / z + b; there is five input variables and they may be changed at every clock. If use combinational logic to synthsize it...
Altera_Forum's avatar
Altera_Forum
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17 years ago

I don't see your example exactly related to the question. It is using different clocks and likely to cause an unclear timing situation while sotusotu had a straightforward synchronous design as it should be. For longer delays (if needed at all), RAM based FIFOs instead of registers could be used, but with a single clock if ever possible.

Furthermore I think your delay examples are not corresponding to typical todays FPGA speed, they rather apply to last millenium types. As said, hardware multipliers can be used preferably.