How to realize the pipeline in mixed operation of the divider or multiplication?

The solution seems correct if multiplier and divider are used without additional pipelining (no clock provided to LPM_MULT or LPM_DIVIDE). I don't know if it already meets your performance requirements then. You also didn't tell about the used hardware. If a family with hardware multiplier is involved, I would expect that no pipeline is needed for the multiplier and first addition (but doesn't harm of course). In contrast, the divider is more likely to need additional pipeline stages.

You should be able to find out the necessary pipeline level at your intended clock speed and word width for each partial operation by preceeding tests and then assemble the complete function with respective delays for the iinvolved operands. It could be written as a parmeterizable design with arrays and for loops also, but it's probably more simple as you did it.

If you are in doubt about the actual pipeline delay of particular MegaFunctions, Quartus Simulator (or ModelSim) can easily clarify it with a numerical test.