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Altera_Forum
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10 years ago

How to make Master module to access the avalon MM slave peripherals

Hi, I am writing code for making the master module to access the avalon MM slave peripherals (e.g. UFM and ADC). But first I need to know that is there any IP available to access these modules ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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Hi,

I am writing code for making the master module to access the avalon MM slave peripherals (e.g. UFM and ADC). But first I need to know that is there any IP available to access these modules (UFM and ADC)?? I dont want to use NIOS II processor as Master because I dont have enough memory. I am using MAX10SAU169C8GES FPGA. What could be the possible solutions??

Thanks in advance for the comments and suggestions.

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You may try to check the following pages to see if can find any related design for reference:

http://www.alterawiki.com/wiki/special:categories

https://www.altera.com/products/intellectual-property/reference-designs.html