Contributorhow to Integrate PCIe DMA to replace USB3 interface
Dear Intel Experts,
I have an evaluation package from TI data acquisition chip AFE58JD48. the original system is 16 ADCs (8 lane of JESD204B, upstream is USB3). I need to expand it to 64 ADCs (16 lane of JESD204B), USB3 is not fast enough, so I need to replace the USB3 module to PCIe3. the original design has interface from USB3 to DDR4 control, and I2C. I start to learn how to use a pcie IP to replace USB3.
Here is the block diagram of the project. 
the idea is to use the pink block to replace the orange block. I do have enough background knowledge of the PCI/PCIe. but I don't know how to integrate the PCIe module through the platform designer.
I start from create a pcie module from the Intel example. which can be complied and simulated by the platform designer created environment.
Here are my questions,
1. Is there a document explain what the default pcie example simulation is doing?
2. To understand the PCIe transfer data to the Memory module and see the signals toggle on the memory bus, how to make the PCIe BFM module initiate a memory write/read command in the pcie example simulation environment?
3. Is there any instruction/suggestion of good practice of the integration?
Appreciate your help.
David
Hi David,
To be honest, I don't not have experience in designing the TI data acquisition before.
But I can share my onboard experience past year ago on how to learn Intel PCIe IP in a quick time.
1. Is there a document explaining what the default PCIe example simulation is doing?
Normally I will refer to the user guide and release note for this.
- If you are preferring to do the PCIe link-up, integration and some debug methods, you may refer to Intel official youtube channel where step-by-step demos are available for learning.
- Integrate design to Platform designer you may refer to video below
- Below are a few videos that I found very useful for myself.
2. To understand the PCIe transfer data to the Memory module and see the signals toggle on the memory bus, how to make the PCIe BFM module initiate a memory write/read command in the PCIe example simulation environment?
- For the BFM memory write/read you may refer to
- I believe the explanation there is far clear than what I explained.
3. Is there any instruction/suggestion of good practice of the integration?
- There is a few link in my highlight browser bookmarks tap which help me to understand Intel FPGA IP
- IP resource center
- Fault Tree Analysis of PCIe, https://community.intel.com/t5/FPGA-Wiki/FTA-PCI-express/ta-p/735993
- Intel PCIe known Issue , https://www.intel.com/content/www/us/en/support/programmable/articles/000078654.html
Hope this is helpful to you at the moment, do you facing any errors in simulating your design?
or any specific question that you need further clarification? If yes, then I am happy to help out.
Regards,
Wincent_Intel
Appreciate your help.
