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I can't really run simulations currently because of modelsim's sinlge-HDL restriction. I'll have to find a way around that..
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Modelsim can handle multiple languages. I use Modelsim-SE.
Modelsim-Altera Edition appears only to support a single language:
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There is an upside of lower cost if SDRAM ends up working out though. These will replace our current products if I ever get that far with it.
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Sure, but you need to exhaustively test your code to ensure that SDRAM can meet that requirement, and you cannot do that without proper simulation tools.
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Getting a clean 640x480 image is only step one in a 30+ step development process.
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And without proper simulation, you're stumbling at step 1.
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As of writing this, the entire system is QSYS-based.
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You have yet to convince me that you are using Qsys correctly. Just mapping your camera and VGA ports to seemingly identically names ports in Qsys does not make them Avalon-MM components.
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I now have to take wild guesses as to what is causing that interlaced look..
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No, you don't. You simulate and you understand, there's no need to guess about anything.
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The camera and VGA entity ended up as "Bridges and Adapters/Streaming" modules which have Avalon Memory Mapped Master interfaces.
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You're just showing your lack of understanding here. That is just a "section" in the IP catalog. It means nothing.
I'm going to stop responding to this thread until you post a simulation of your VGA and camera interfaces showing that they implement Avalon-MM master interfaces.
Modelsim Altera Starter Edition is free, and you should be able to take your existing single-language code and either convince me the interfaces can be mapped to Avalon-MM interfaces or already adhere to the Avalon-MM requirements.
Good luck!
Cheers,
Dave
Honored Contributor
