How to implement DE0 SDRAM as 2-port RAM

There are no packets or other data that can be reliably grouped or streamed. There are two different entities requesting to read and write from unpredictable addresses at unpredictable times usually simultaneously. So far I've created the QSYS component for the camera. I think I picked bridges and adapters/Avalon ST. It ended up being a memory master though after I set all of the parameters.. I messed up and made all the exports reside under one conduit name but other than that it might work.. I have a feeling I can't just connect the two masters to the SDRAM controller and trust that it will just 'figure' it out. There is probably some component that needs to handle that.. It would set priority like you mentioned earlier.. Any idea what component that would be? Maybe a frame buffer? I hope not because I want to be able to store and retrieve all sorts of other data using this SDRAM chip and random times..