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Altera_Forum
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11 years ago

How to implement DE0 SDRAM as 2-port RAM

I currently use the tiny bit of memory on the FPGA for a computer vision project but it's way too limited. I have a stand-alone SDRAM controller from Altera (partially pasted below) but I need one mo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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When creating a new component in QSYS, I'm having trouble guessing which group needs to be selected.

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That is not quite how creating a Qsys component works.

You first have to determine *if* the bus interface used by your component is compatible with the Avalon-MM specification, i.e., whether its use of the address, read, write, and data correspond to the Avalon-MM use of those signal names. If it does not, then you have to create bridge logic that maps the transactions. That bridge might incorporate a FIFO (to handle bursts or latency).

So my first question is, do you have a simulation for your VGA bus interface and your camera controller? If not, you should really write one :)

Cheers,

Dave