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When creating a new component in QSYS, I'm having trouble guessing which group needs to be selected.
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That is not quite how creating a Qsys component works.
You first have to determine *if* the bus interface used by your component is compatible with the Avalon-MM specification, i.e., whether its use of the address, read, write, and data correspond to the Avalon-MM use of those signal names. If it does not, then you have to create bridge logic that maps the transactions. That bridge might incorporate a FIFO (to handle bursts or latency).
So my first question is, do you have a simulation for your VGA bus interface and your camera controller? If not, you should really write one :)
Cheers,
Dave
Honored Contributor
