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Altera_Forum's avatar
Altera_Forum
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10 years ago

How to implement DE0 SDRAM as 2-port RAM

I currently use the tiny bit of memory on the FPGA for a computer vision project but it's way too limited. I have a stand-alone SDRAM controller from Altera (partially pasted below) but I need one mo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Using QSYS, I corrected the SDRAM size to 8Mb by correcting hte row and column sizes, fixed the the clock frequency, removed JTAG, added a 100MHz clock generator, and exported it to VHDL. It looks like it will work but I'm still messing with it...