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Altera_Forum
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11 years ago

How to implement DE0 SDRAM as 2-port RAM

I currently use the tiny bit of memory on the FPGA for a computer vision project but it's way too limited. I have a stand-alone SDRAM controller from Altera (partially pasted below) but I need one mo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Method 1 is fine except that JTAG is still in there

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No its not. Look at the file qsys_system_sdram.v, it is *ONLY* the SDRAM controller component.

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and the address size is only 13bit which seems way too short for 8Mb. Also the ram size hasn't been changed. The column and row values may also be wrong.

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That would be the "Ignore the fact that the DE0 may have different SDRAM". If you edit the SDRAM controller parameters to match those on the DE0 and then "Generate" the system, the generated .v file will have the parameters you need.

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1. For WRAPPER GENERATION METHOD# 2, why remove the clock? Why not leave the clock and SDRAM and just remove the JTAG component?

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Now you are starting to see the possibilities :)

Cheers,

Dave