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Altera_Forum
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10 years ago

How to implement DE0 SDRAM as 2-port RAM

I currently use the tiny bit of memory on the FPGA for a computer vision project but it's way too limited. I have a stand-alone SDRAM controller from Altera (partially pasted below) but I need one mo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I finally had time to get back to this.

Method 1 is fine except that JTAG is still in there and the address size is only 13bit which seems way too short for 8Mb. Also the ram size hasn't been changed. The column and row values may also be wrong.

1. For WRAPPER GENERATION METHOD# 2, why remove the clock? Why not leave the clock and SDRAM and just remove the JTAG component?