How to implement a FIR filter with the ALTSHIFT_TAPS megafunction

ALTSHIFT_TAPS is based on FPGA internal RAM. I suggest to think a bit about the principle restrictions of RAM based FIR designs. Basically, they can't read more than two locations per clock cycle for a single RAM block (using the dual port feature). Implementing fast shift registers with many taps means using many RAM blocks, that are only partly populated. You'll fastly run out of RAM resources this way.

The Altera FIR MegaFunction is a good example how different storage options, both for data and coefficients can be chosen depending on the filter data rate. Even if you want to implement your own FIR design, reviewing the structures suggested by the FIR compiler can be quite instructive.