Forum Discussion
JohnT_Altera
Regular Contributor
4 years agoHi Kevin,
What are your views wrt the counter I added ?
If the user does not program the flash and delays this passing the time when pfl_nreset goes back high, the system will fail to configure the FPGA.
I suspect that the PFL is performing something that cause the system will fail to configure the FPGA. Will need to monitor all the signal to understand what is actually happening.