how to efficiently drive async SRAM?

I managed to shuffle my PLL resources around to free a clock, now I can generate a higher duty cycle signal for my write clock, now can do one write per cycle.

But I'm struggling on a different front: Not really having understood constraints, my external timing seems unreliable. In theory there should be enough timing headroom, but in fact the design is unstable, varies per synthesis. I've read about set_input_delay, set_output_delay, set_min_delay, set_max_delay but am unsure how to use them. Which are really affecting the timing, which are just informative to the fitter how tight a path is?

Maybe the point here is that the SRAM is asyncronous (has no clock), it's not really clock to output delay that matters, it's the timing of the outputs towards each other, or in case of a read access the timing of outputs to readback of inputs. How can I design for this?

Jörg