Honored Contributor
Honored ContributorI'd like to wrap up my thread, since the internet is so full of dangling threads with the silently found answer never told...
I ended up writing my own SRAM controller as an Avalon slave, skipping the tristate bridge. It is (admitted) pretty tailored to my case, but perhaps it can serve as an example: http://welecw2000a.svn.sourceforge.net/viewvc/welecw2000a/fpga/nios2/altera/ip/w2000_ext_ram_bus/ext_bus.v?revision=708&view=markup The performance "trick" is overlapped pipelining, issue the next one or two reads even before the result of the first arrives. This depends on the clock rate, a given pipeline depth (and perhaps read phase) only works for the frequency being designed for. So I have latency, but get a data word for each clock cycle. Pretty much like a burst. For writing, I have an issue to shape a suitable write pulse for every clock cycle, by e.g. combinatoric with the clock level to get a half cycle pulse. The pulse is probably too short. Right now I use alternating wait states and toggle the write, giving me half the performance. Suggestions welcome... Unfortunately I'm out of PLL resources to generate aux clocks. But overall, it's way better than the stock IP, 3 times faster on read, probably still faster on write. Jörg
