how to efficiently drive async SRAM?

Thanks,

While being too impatient (:-P) I already started writing my own controller, as an Avalon slave. The pity with that is I can't even use the tristate bridge any more, since it seems not passing waitrequest. This is bad for the other chip on the external bus, instead of just attaching another tristate slave component I'll have to write that part by myself, too.

For I test, I only implemented reading by rather directly passing signals. It *almost* works with zero waitstates. Only some disturbance on the LCD screen, which is a continuously reading bus master. :unsure:

So you're right, I need a leadoff cycle, but by pipelining the read I will still be able to read one word per clock. I wonder if it would be helpful to make it a bursting controller. Is a leadof cycle enough penalty to make this a net win?

The fixed read and write cycles are suboptimal, don't give enough control. For example, reading works without a "setup time" cycle, but writing doesn't. However this can't be independently configured.

So far, I still stand to say that Altera supports async SRAMs not well...

Jörg