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Usually the tse sopc sdc file is enough. Then you only need to constrain your input clock and PLLs outputs, which drive your mac rx/tx clock ports.
I'm not an Ethernet guru but I think the extra FF in the preamble is not a problem, since the mac should discard symbols until it receives a complete the preamble sequence (and this eventually arrives correctly, isn't it?); when the preamble has been received the mac will receive the actual data payload.
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Unfortunately, even if the complete preamble sequence eventually arrives correctly (verified by signalTap), the extra "ff" ahead of correct preamble sequence does bring me trouble. After I read statistics counter with address 0x074 (aAlignmentErrors counter) from MAC, I found MAC treat this frame as frame with alignment error and discard it.
I am not sure whether adding rx_clk delay to the PHY by programming bit7 of mdio register 20 (Marvell 88E1111) will remove the extra "ff" since according to my understanding, adding rx_clk delay by 2ns (setting bit7 to 1), the rx_clk can still sample one "f" instead of two "ff" (since "ff" will last one entire clock cycle, which is 8ns, delay rx_clk by 2ns will sample at least one "f"). Can anybody tell me how to remove the additional "ff"?
FYI, I am using RGMII interface and the rx_clk is 125MHz, generated from PHY.
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