How to constrain tse on cyclone III board

I just had a look at the Altera example for the Cyclone III dev board, and amazingly they don't put any timing constrains on the RGMII interface... Not good for a "design example" ;)

You can use those .sdc files from the uCLinux reference design from the Nios wiki.

There are two PHY registers that you can change in the Marvell PHY to specify that the receive and transmit data should be center-aligned with the clock rather than edge-aligned. I don't remember the registers addresses, but you should find them by doing a search on the forum. I don't remember what the Altera TSE driver is doing when initializing the Marvell PHY.