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it should be a lot faster with on chip ram... Is this ram shared with something else?
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Nope, the on-chip 32-bit wide memory is connected only to the master template. I took a snapshot of what I'm seeing..
basically I have a 100Mhz state machine that whenever a 10Mhz data clk goes high, I increment the data, and the address (by 4), and set the data valid/go pulse high (the write length is constant at 4. This addr/data is presented half a clock after dataclock goes high.
At this point these signals to the master template don't change until just before the next data clock.. at which time I deassert go, and wait for the next data clock to present the new data.
When I pause the template/Nios to look at the onchip memory, the transfers are taking place as evident by the incrementing data, however, instead of 1 new value per location, I see new data being written into 6 consecutive addresses. On signaltap I see the addresses correctly incrementing by 4 (32-bit data) and the data incrementing by 1. However the on chip memory is not incrementing by 1 at every address.
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