How to compile 2 PCIe instances in one project

HI Pavel,

Thanks for sharing the PCIe debug design.

Debug finding shown later PCIe design somehow overwrite top PCIe design causing synthesis error. All depends on the file sequence in Quartus project

1. Scenario 1 : Quartus project file sequence with pcie_spi design at top follow by pcie_ddr at bottom
2. result = Quartus synthesis error complaining elaboration failure in pcie_spi
3. Scenario 2 : If switch Quartus project file sequence to pcie_ddr design at top follow by pcie_spi at bottom
4. result = Quartus synthesis error complaining elaboration failure in pcie_ddr

screenshot explanation is attached in earlier post.

This looks like a bug, I have filed investigation report to Intel Engineering to look into issue.

Will keep you posted on the update.

Additional comment :

1. Side note : You may want to comment out unnecessary PCIe internal signals to avoid end up pulling few hundred over signals to your top level design file - signal port declaration. This will overwhelm Quartus fitter compilation later
2. Unfortunately Quartus Standard and Quartus Pro each has different IP design file structure so they are not compatible to each another. You need to pick one for your design development
3. Schematic design is not preferred anymore as FPGA design getting more complicated. It's hard to create/modify schematic design with few hundred design connection. If you like block diagram view, you can always use the "RTL viewer" feature in Quartus to generate block diagram view of your design

Thanks.

Regards,

dlim