How to add Intel IP to Custom IP (hw.tcl)?

You can use callback feature. refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-platform-designer.pdf page 118

I don't know how that should help me. Can you please give me an example? In my understanding it is only about a selection of files, but how to add the IP.

By the way, I fixed ALT_IOBUF. The synthesis was ok with it, but for simulation it has to be written lowercase "alt_iobuf".

However, altclkctrl is inserted automatically during synthesis, but not for simulation. If I create a megafunction IP, then I dont know how to add it. The same thing with the FIFO.

I tried to add the .sip, but that file is only copied which does not help the simulator.

Have you read the document on the call back feature? There is a posted example code there that you follow. Let me know if you don't understand how to use the feature.

any update?

Unfortunately, that example you gave me only showed how to add some .v or .sv files.

I need a example for a structure like that:

• top_file.v
  • file_a.v
  • file_b.v
  • ALTCLKCTRL (what I have to add?)
  • file_c.v
    • file_cc.v
    • Altera DC_FIFO_IP (what I have to add?)

Adding the verilog files is clear, but what to do with the IPs? Is there a way to add .qsys or _hw.tcl?

Workaround ALTCLKCTRL: Fortunately, the synthesis creates the clock switch by itself. However for simulation, I had to make a extra simulation file, because it was not found there.

I think that way is still not best-practice.

Nope, it is not an example to add .v or .sv files.

If you refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-platform-designer.pdf page 122 example 18.

it shows you an example of how to add an Emif instance using the IP. This include on how you should create it in the .v and the hw.tcl.

with this example, you can use it for the altclkctrl as specified in your above.

How was the example above goes? does it helps?