how to access the on-chip fifo with my logic module for ST interface

I think I find out the issue:

module subfifo_fifo_0 (

// inputs:

avalonmm_write_slave_address,

avalonmm_write_slave_write,

avalonmm_write_slave_writedata,

avalonst_source_ready,

rdclock,

rdreset_n,

wrclock,

wrreset_n,

// outputs:

avalonmm_write_slave_waitrequest,

avalonst_source_data,

avalonst_source_valid

)

;

output avalonmm_write_slave_waitrequest;

output [ 31: 0] avalonst_source_data;

output avalonst_source_valid;

input avalonmm_write_slave_address;

input avalonmm_write_slave_write;

input [ 31: 0] avalonmm_write_slave_writedata;

input avalonst_source_ready;

input rdclock;

input rdreset_n;

input wrclock;

input wrreset_n;

wire [ 31: 0] avalonmm_map_data_in;

wire avalonmm_write_slave_waitrequest;

wire [ 31: 0] avalonst_map_data_out;

wire [ 31: 0] avalonst_source_data;

reg avalonst_source_valid;

wire [ 31: 0] data;

wire [ 31: 0] q;

wire rdclk;

wire rdempty;

wire rdreq;

wire wrclk;

wire wrfull;

wire wrreq;

wire wrreq_driver;

//the_dcfifo_with_controls, which is an e_instance

subfifo_fifo_0_dcfifo_with_controls the_dcfifo_with_controls

(

.data (data),

.q (q),

.rdclk (rdclk),

.rdempty (rdempty),

.rdreq (rdreq),

.wrclk (wrclk),

.wrfull (wrfull),

.wrreq (wrreq),

.wrreset_n (wrreset_n)

);

//in, which is an e_avalon_slave

assign avalonmm_write_slave_waitrequest = wrfull;

//the_map_avalonmm_to_avalonst, which is an e_instance

subfifo_fifo_0_map_avalonmm_to_avalonst the_map_avalonmm_to_avalonst

(

.avalonmm_data (avalonmm_map_data_in),

.avalonst_data (avalonst_map_data_out)

);

assign wrreq_driver = (avalonmm_write_slave_address == 0) & avalonmm_write_slave_write;

assign avalonmm_map_data_in = avalonmm_write_slave_writedata;

assign wrreq = wrreq_driver;

assign data = avalonst_map_data_out;

assign wrclk = wrclock;

assign rdclk = rdclock;

assign avalonst_source_data = q;

assign rdreq = !rdempty & avalonst_source_ready;

always @(posedge rdclk or negedge rdreset_n)

begin

if (rdreset_n == 0)

avalonst_source_valid <= 0;

else

avalonst_source_valid <= !rdempty & avalonst_source_ready;

end

//out, which is an e_atlantic_master

endmodule