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Altera_Forum's avatar
Altera_Forum
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13 years ago

how to access the on-chip fifo with my logic module for ST interface

I add a on-chip fifo in Qsys(see the attached figure), one interface is Avalon MM for nios2 access,and another interface is ST source for my logic . and the ST source's signals : ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I have tested the on-chip fifo ,with avalon mm write port and st read port

when I assert the ready high for st read port,the write data to avalon mm port

will go through the st port, and the valid signal keep low(I use it to trigger a

vhdl module with its rising edge,but not active ),why?

thanks for your help!