Forum Discussion
Nooraini_Y_Intel
Frequent Contributor
8 years agoHi SrLam9,
I have attached an example project design I just tested today on Arria 10 dev kit which works. You can refer to the rsu_cb.vhd which I wrote the parameters to read reconfiguration status register and write the AnF, disable watchdog timer and application image boot address. After power up the board (of course EPCQL was programmed with a .jic before), when I check using SignalTap to read the reconfiguration status register, I can observe the data_out[31..0] show 00000. You can try to check the rsu_cb.vhd and compare with yours.
Regards,
Nooraini