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corestar
Contributor
ContributorHow does Qsys compute BAR sizes for Avalon-MM PCIe?
I'm attempting to use the "Avalon-MM Cyclone V Hard IP for PCI Express" core. I created an example design modeled after: C:\intelFPGA_lite\19.1\ip\altera\altera_pcie\altera_pcie_cv_hip_avmm\example_...
- Hi,
BAR sizes are defined by the address map. Review chapter "Minimizing BAR Sizes and the PCIe Address Space" in Cyclone V AVMM for PCIe user manual.
corestarContributor
ContributorPartially figured it out myself. It's apparently not allowed to export the Rxm_BARX and Txs buses. It's clumsy, but I created Avalon to External Bus Bridge to connect to the Rx buses and an "External Bus to Avalon Bridge" for the Tx bus. The BAR sizes match the address sized in the bridge.
Still does not explain the example ep_g1x1.qsys where BAR0 is connected to a 4 KB block RAM and yest has a size of 4 MB.
FvM
Super Contributor
Super ContributorHi,
BAR sizes are defined by the address map. Review chapter "Minimizing BAR Sizes and the PCIe Address Space" in Cyclone V AVMM for PCIe user manual.
BAR sizes are defined by the address map. Review chapter "Minimizing BAR Sizes and the PCIe Address Space" in Cyclone V AVMM for PCIe user manual.
