How do you configure the pcie root port on the Stratix 10 to allow the HPS to map an I/O BAR?

Hi,

I take a deep look at it, the Rootport for AVMM configuration is support IO read and write via CRA port.

https://www.intel.com/content/www/us/en/support/programmable/articles/000077505.html

if refer to the rocketboard website , you can try to configure it by using the address offset.

https://www.rocketboards.org/foswiki/Projects/Stratix10PCIeRootPortWithMSI

Also, friendly reminder, the root port testbench is not available for AVMM..

• Stratix 10 Avalon-MM Interface for PCI Express Solutions User Guide

Hope this answering your question. Let me know if you need any further clarification.

Regards,

WIncent_Intel