New Contributor
Regular Contributor
Hi,
I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket
Regards,
Wincent_Intel
New ContributorWincent, my problem has not been solved. I don't think the question has been understood. Let me try another direction. Look back at those address' back in the linux-side device tree that you posted your very first response:
ranges = <0x81000000 0x0 0x00000000 0x00010000 0x00000000 0x00010000>,
<0x82000000 0x0 0x00000000 0x00010000 0x00000000 0x00010000>;
You added the line that starts with an 0x81000000, which is correct, because that declares an I/O BAR. Now look at the red highlighted 64-bit addresses. These point to an address of the pci bus controller. They can't be the same thing. They also must have a backing on the FPGA side created by the PCIe IP. This backing exists for the second line that declares a MEM bar, which is called the txs or hptxs on the FPGA side. But the backing does not exist for the first line. The whole point of this question is how to make a compatible IO space on the FPGA side so that I can point to it with that 0x81 line from the device tree.
