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bralston7's avatar
bralston7
Icon for New Contributor rankNew Contributor
3 years ago

How do you configure the pcie root port on the Stratix 10 to allow the HPS to map an I/O BAR?

I need help configuring the pcie root port on the Stratix 10 to allow the HPS to map an I/O BAR?. I started out with the Rocketboards Pcie example (https://www.rocketboards.org/foswiki/Projects/Strat...
bralston7's avatar
bralston7
Icon for New Contributor rankNew Contributor
3 years ago

While I appreciate the follow-up, that is just a diagram from the PCI spec. It doesn't tell me anything about making this work in the Intel PCIe IP component for Stratix 10. The Platform Designer GUI does not have the granularity or visibility to the command status registers.

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

If refer to the document Stratix 10 Avalon-MM Interface for PCI Express Solutions User Guide, under Figure 73 there is I/O space address map. Refer to 10.4.3, there are steps to configure the Root Port and Endpoint Configuration Space registers before you issue transactions to the Endpoint. Step 3a mentions that the I/O is assigned in the Endpoint BAR register. Hence, you do not need to assign the I/O bar address on the rootport. The Root Port BFM does not support accesses to Endpoint I/O space BARs.

Regards,

Wincent_Intel