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bralston7's avatar
bralston7
Icon for New Contributor rankNew Contributor
3 years ago

How do you configure the pcie root port on the Stratix 10 to allow the HPS to map an I/O BAR?

I need help configuring the pcie root port on the Stratix 10 to allow the HPS to map an I/O BAR?. I started out with the Rocketboards Pcie example (https://www.rocketboards.org/foswiki/Projects/Strat...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


the IO Space enable is at bit[0] of command register.

Can you please try it out and see if you are able to do that ?


Regards,

Wincent_Intel


  • bralston7's avatar
    bralston7
    Icon for New Contributor rankNew Contributor
    3 years ago

    Sorry, I cannot see where I could possibly do that in Platform designer. I can't find anything resembling 'command register' on the PCIe IP settings

    Did you look at my screenshot? Could you show me a screenshot of what you are looking at?

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      3 years ago

      Hi,

      Please ignore my previous message as different version of quartus and different design might have different approach.
      I share the IO Space enable is at bit[0] of command register to you.

      Is it answering your question ?

      Regards,

      Wincent_Intel