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bralston7's avatar
bralston7
Icon for New Contributor rankNew Contributor
3 years ago

How do you configure the pcie root port on the Stratix 10 to allow the HPS to map an I/O BAR?

I need help configuring the pcie root port on the Stratix 10 to allow the HPS to map an I/O BAR?. I started out with the Rocketboards Pcie example (https://www.rocketboards.org/foswiki/Projects/Strat...
bralston7's avatar
bralston7
Icon for New Contributor rankNew Contributor
3 years ago

Thank you for the response. I've had the device tree side all worked out for a bit now, but its what you describe in 1) is what I am missing. There is no root port tab in Qsys Designer (yes, my type is set to Root Port, not Endpoint), and no checkbox anywhere for "I/O Space Enable". Ive been all over that GUI and I can't find it. There's no way a full implementation of a PCI root port IP doesn't include a way to make an IO space. How could they leave something like that out? There is an I/O space described in the documentation (ug_s10_pcie_avmm.pdf) called the CRA, but it appears to have a specific purpose for the driver, and not for creating an I/O space.

Could you please reach out to somebody who is intimately familiar with the PCIe IP?

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

Which varient of Stratix 10 board you are testing on ? GX or SOC version ?

Regards,

Wincent_Intel

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi,

    Just to confirm that the step is correct to enable the IO space.
    Can you please check and let me know if you still cannot get it ?

    1. Open the Quartus Prime software and open your project.

    2. Open the "Platform Designer" tool by clicking on "Tools" > "Platform Designer".

    3. In Platform Designer, click on "System" in the left-hand pane, and then click on the "System Info" tab.

    4. Under the "Address Spaces" section, find the "I/O" row and check if the "Enable" column is set to "Yes". If it is already set to "Yes", then I/O Space is already enabled.

    5. If the "Enable" column is set to "No", click on the pencil icon to edit the I/O address space.

    6. In the "Edit I/O Space" dialog box, check the "Enable I/O Space" box, and then click "OK".

    7. Save the Platform Designer design and exit.

    8. In Quartus Prime, recompile the project and program the FPGA with the updated design.

    Looking forward to hear back from you. Please let me know if you are unable to get the feature.
    Regards,

    Wincent_Intel